如何将Virtex-5 I/O引脚用于差分对输入?

最常见的用法是I / O标准LVDS_25，它使用2.5V Vcco作为存储区。
同
在此标准中，您可以启用“DIFF_TERM”以在100欧姆之间终止接收器
真实和补充输入垫。
在差分输入的所有情况下，您必须实例化
输入缓冲区 - 通常是“IBUFDS”。
Virtex 5 HDL设计的库指南展示了如何实现
为Verilog和VHDL实例化IBUFDS。
请注意，LVDS也可在银行上使用
使用3.3V Vcco（LVDS_33）但在这种情况下DIFF_TERM选项不可用。
它始终是
最好将片内匹配用于高速LVDS输入，因此我将避免使用LVDS_33
输入。
-  Gabor
-  Gabor



以下为原文

The most common usage is I/O standard LVDS_25, which uses 2.5V Vcco for the bank.  With
this standard you can enable "DIFF_TERM" to terminate the receiver with 100 ohms between
true and complement input pads.  In all cases for differential inputs, you must instantiate the
input buffers - usually "IBUFDS".  The libraries guide for Virtex 5 HDL designs shows how to
instantiate the IBUFDS for both Verilog and VHDL.  Note that LVDS is also available on banks
with 3.3V Vcco (LVDS_33) but in that case the DIFF_TERM option is not available.  It is always
best to use the on-chip termination for high speed LVDS inputs, so I would avoid using LVDS_33
for inputs.
 
-- Gabor
-- Gabor

您可以从GUI上的语言模板（灯泡按钮）获取编码示例（请参阅下面的快照）：
saima_ishtiaq84写道：
嗨......任何人都可以指导我如何将Virtex-5 I / O引脚用于差分对输入???
在这种情况下如何终止发射器和接收器????
我必须使用Verilod HDL编写代码。
等待回应..
干杯，吉姆



以下为原文

You can get coding examples from the language templates (the light bulb button) on the GUI (see the snapshot below):
 

 

saima_ishtiaq84 wrote:
hi...can anybody guide me how Virtex-5 I/O pins can be used for differential pair inputs??? How transmitter and receiver will be terminated in that case???? I have to write code using Verilod HDL. waiting for response..

 
Cheers,
Jim

嗨......任何人都可以指导我如何将Virtex-5 I / O引脚用于差分对输入???
在这种情况下如何终止发射器和接收器????
建议（除了Gabor和Jim的帮助）：
查找Virtex-5开发板，其中包含FPGA的差分输入信号和FPGA的差分输出信号。
下载开发板FPGA的参考设计“项目”。
查看顶级源代码和.UCF文件，了解差分输入和差分输出的实现示例。
然后下载并查看电路板原理图，以获得源代码和.UCF文件中检查的信号的详细板级实现。
本练习不会教你很多关于你可以选择的限制和选择范围（其中一些是由Gabor描述的），这将需要你的一些阅读。
但它为您提供了一个可行的，真实的示例，您可以从中开始扩展您对Virtex-5功能的理解。
通过回顾现有的丰富且易于获得的设计实例，可以学到很多东西。
如果您尚未安装Document Navigator，建议您阅读新用户论坛自述文件线程以获取DocNav的说明。
它是回答诸如你的问题的非常有用的工具。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
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我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

hi...can anybody guide me how Virtex-5 I/O pins can be used for differential pair inputs??? How transmitter and receiver will be terminated in that case????
 
Suggestion (in addition to the helps from Gabor and Jim):

• Find a Virtex-5 development board with differential input signals to the FPGA and differential output signals from the FPGA.
  

• Download a reference design 'project' for the development board FPGA.
  

• Look at both the top-level source code and the .UCF file for implementation examples of differential input and differential output.
  

• Then download and review the board schematics for detailed board-level implementation of the signals examined in the source code and .UCF file.
  

This exercise will not teach you very much about the limits and range of options which are available to you (some of which are described by Gabor), this will require a bit of reading on your part.  But it gives you a working, real-world example from which you can start expanding your understanding of Virtex-5 capabilities.  Much can be learned by reviewing existing design examples which are plentiful and readily available.
 
If you do not already have Document Navigator installed, suggest you read the New Users Forum README thread for a description of DocNav.  It is a very useful tool for answering questions such as yours.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
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2. Search the forums (and search the web) for similar topics.
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