如果两个FPGA连接在单个JTAG链中那么DONE和INIT引脚的推荐连接是什么

每个FPGA系列的配置用户指南中都讨论了INIT_B和DONE引脚。
通常，每个FPGA的INIT_B引脚独立上拉至配置组的VCCO。
如果您认为可能存在开机电源稳定性问题，那么您可能需要使用“电源良好”信号来阻止配置。
如果您希望所有设备在配置结束时一起开始运行，那么您将DONE引脚连接在一起，如果无关紧要，那么DONE引脚可以是独立的。
在任何一种情况下，在DONE上使用强上拉（200-400ohm）到配置组的VCCO，或者在最后一个设备上配置DRIVEDONE的比特流选项。
这是为了确保DONE信号的上升时间小于一个CCLK周期。
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以下为原文

INIT_B and DONE pins are discussed in each FPGA family's Configuration User Guide.
 
In general, INIT_B pins of each FPGA are independently pullup up to the VCCO of the configuration bank.  If you think that you may have power-on power supply stability issues then you may want to use a "power good" signal to hold off configuration. 
 
If you want all devices to start operating together at the end of configuration then you connect the DONE pins together, if it doesn't matter then the DONE pins can be independent.  In either case, use either a strong pullup (200-400ohm) on DONE to the VCCO of the configuration bank, or the bitstream options of DRIVEDONE on the last device to be configurated.  This is to ensure that DONE signal has a rise time of less than one CCLK cycle. 
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情况1：
在设计中，INIT引脚通过上拉连接在一起，并且完成的引脚通过上拉连接在一起。
在这种情况下，通电后两个引脚始终为低电平。
通过JTAG进行配置永远不会发生。
案例2：
当INIT引脚分离（仍然将引脚连接在一起）时，可以配置FPGA。
配置流程（程序FPGA1（完成信号低且FPGA1未配置） - >程序FPGA2（完成信号高且FPGA2单独配置） - >再次编程FPGA1（完成信号为高电平且FPGA1配置））
最后我可以看到两个FPGA都配置好了。
有任何想法吗 ？



以下为原文

Case1:
In the design, INIT pins are tied together with a pullup and done pins are tied together with a pullup. In this case, both pins are always low after powered up. And configuration through JTAG is never happen.
 
Case2:
When INIT pins are separated (still done pins are tied together), FPGAs can be configured.
 
Configuration flow (program FPGA1 (Done signal is low and FPGA1 not configured) -> Program FPGA2 (Done signal is high and FPGA2 alone configured) -> again program FPGA1 (Done signal is high and FPGA1 configured))
 
Finally I can see both FPGAs are configured.
 
Any ideas ?

情况1：
听起来像PCB问题。
检查原理图，确保将INIT引脚连接到PULLUP的网络没有连接到其他任何东西，并检查PULLUP电阻两侧的电压。
案例2：
在BITGEN中生成BIT文件时，尝试在最后一台设备上设置DRIVEDONE，在第一部分设置DONEPIPE。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
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以下为原文

Case 1:
Sounds like a PCB issue.  Check the schematic to ensure that the net connecting the INIT pins to the PULLUP isn't connected to anything else and check the voltages on both sides of the PULLUP resistor.
 
Case 2:
Try setting DRIVEDONE on the last device and DONEPIPE on the first part when the BIT files are generated in BITGEN.
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我尝试了这些建议。
但两种情况都有相同的结果（case1-未配置，case2  - 相同的配置流程）。
但是如果配置完成信号是分开的，那么FPGA就会被配置（一次任何FPGA）。



以下为原文

I tried the recommendations. But both the cases have same results (case1 -not configured, case2 - same configuration flow). But if the configuration done signals are separated, then FPGAs are getting configured (any FPGA at a time).

您使用的是冲击和xilinx电缆还是其他什么？
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
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以下为原文

Are you using impact and a xilinx cable or something else?------Have you tried typing your question into Google?  If not you should before posting.
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使用Impact 11.5＆amp;
Xilinx平台电缆USB



以下为原文

using Impact 11.5 & Xilinx platform cable USB

您所观察到的内容没有任何意义，它应该与连接的两个DONE引脚配合使用。
您使用的是哪些FPGA？如何在测试中组合和分离DONE信号？
还有其他与DONE引脚相连的东西吗？
您是否使用默认属性生成BIT文件？
或者你在设置额外的选项？ 
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

What you are observing doesn't make any sense and it should be working with the two DONE pins connected.   
 
Which FPGAs are you using?
How are combining and separating the DONE signals in your test?
Is there anything else connected to the DONE pin?
Are you generating the BIT files with default attributes?  or are you setting extra options?
 
 
 
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您使用的是哪些FPGA？
XC6SLX150-2FGG484CES
如何组合和分离
在您的测试中完成信号？
通过安装和不安装串联端接的电阻器。
还有什么东西连接到了 
DONE针？
没有
您是否使用默认值生成BIT文件
属性？
或者你在设置额外的选项？
是的，使用默认属性，也尝试使用上一个消息中建议的bitgen选项。



以下为原文

 
Which FPGAs are you using?
XC6SLX150-2FGG484CES

How are combining and separating the DONE signals in your test?
By mounting and un mounting the resistors which series terminated.
 
Is there anything else connected to the DONE pin?
None
 
Are you generating the BIT files with default attributes?  or are you setting extra options?
Yes, with default attributes, Also tried with bitgen options as you recommended in previous message.
 
 
 

连接两个DONE引脚的电阻值是多少？ 
- 在组合的情况下，你还有一个电阻到VCCO？
如果是这样，有什么价值？
在单独的情况下，用于连接VCCO的电阻值是多少？
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
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以下为原文

What is the value of the resistor that connects the two DONE pins in the combined?
   - In the combined case do you also have a resistor to VCCO?  If so, what value?
What is the value of the resistors used to connect to VCCO in the separate case?
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