如何评估HDL代码的标量以进行算术描述

嗨，
两个月的时间并不多，但除了必须实现多种算法（并将它们连接到系统？）之外，您还应该看一下性能目标。
它是否具有最高性能？
然后算了吧。
您的设计师需要测试不同的方法，这会花费时间。
绩效目标是否温和？
获取EDK并使用MicroBlaze或PowerPC，然后编译算法。
或者，如果你喜欢“无风险无趣”的方式......使用C-Synthesis工具。
这样您就可以提供真正的硬件IP核，并且您可以轻松地检查自适应算法模型与原始代码。
除了接口之外，打算在处理器上运行的算法很少在硬件上开箱即用，因此您需要进行修改。 
有一个很好的综合 
Eilert
在原帖中查看解决方案



以下为原文

Hi,
two months is not much time, but besides the fact that you have to implement several algorithms (and connect them to a system?) it would be interesting for you to look at the performance goals.
 
Has it to be highest possible performance? Then forget it. Your designers need to test different approaches, which costs time.
 
Is the performance goal moderate?  Get the EDK and use a MicroBlaze or PowerPC and just compile the algorithms. 
 
Or if you like it the "no risk no fun" way...use a C-Synthesis tool. This way you can provide true hardware IP-Cores and you can easily check the adapted algorithm models vs. the original code. 
Besides the interfaces, algorithms that are intended to run on processors rarely work out-of-the-box on hardware, so you need to do modifications.
 
  Have a nice synthesis
    Eilert
View solution in original post

lidaxjtu写道：如何评估和计算HDL代码的标量为算术描述（可能是伪代码或某些C源代码），还有设计工作量？
谢谢。 
利达 
我意识到英语不是你的第一语言，甚至是第二语言，但上面的语句让我的解析器扔了一根棒！
----------------------------是的，我这样做是为了谋生。



以下为原文

lidaxjtu wrote:
How to evaluate and calculate the  scalar of HDL  code for an arithmetic description(may be  pseudocode or some C source code),and also the design workload?
thanks.
                                              LiDa

I realize that English is not your first, or even second, language, but the above statement caused my parser to throw a rod!
----------------------------Yes, I do this for a living.

我的意思是如何计算一些软件源代码中描述的算法的VHDL代码量，并确认VHDL中的设计调度。
明白了吗？
谢谢。 
利达



以下为原文

I means that how to calculate the amount of code in VHDL for an algorithm which has been described in some software source code , and also confirm the scheduling of the design in VHDL.
Is that clear?
thanks.
                                              LiDa

恐怕无法直接计算代码量
我觉得你不应该担心代码量而不是“
FPGA中算法的逻辑资源“。
即使是
计算逻辑资源，你需要考虑硬件点
视图。
就像算法所需的总内存位数一样
组合逻辑和寄存器需要然后选择FPGA
家庭和取代选择家庭的设计。
FPGA怪胎



以下为原文

I am afraid there is no way to directly calculate the amount of codeand I feel you shouldn't worry about amount of code rather than the "logic resources for the algorithm in FPGA ".
Even forcalculating logic resources, you need to think in hardware point ofview. like the total bit of memory that the algorithm requires, numberof combinational logic and register requires and then choosing the FPGAfamily and substituting the design in the choosen family.FPGA freak

但是有一个关于我必须做的设计项目的评估，两个月内将在VHDL ip内核中设计几种算法，我想知道这项工作的可能性以及所需的VHDL设计人员数量。
如果我们无法完成，我们可能会提交新的时间表或报告以放弃该任务。 
利达



以下为原文

But there is an evaluation about a design project I have to do,several algorithms will be designed in VHDL ip cores in two months,I want to know the possibility of this work and number of VHDL designers needed. If we can't complete it, we may submit a new schedule,or a report to abandon the task.
                                                                                                                                                                                                         LiDa

是啊。
我同意这是困难的部分。
任何其他人都可以指导我们。
FPGA怪胎



以下为原文

Yeah. I agree this is the difficult part. Can any other guide us on this.FPGA freak

嗨，
两个月的时间并不多，但除了必须实现多种算法（并将它们连接到系统？）之外，您还应该看一下性能目标。
它是否具有最高性能？
然后算了吧。
您的设计师需要测试不同的方法，这会花费时间。
绩效目标是否温和？
获取EDK并使用MicroBlaze或PowerPC，然后编译算法。
或者，如果你喜欢“无风险无趣”的方式......使用C-Synthesis工具。
这样您就可以提供真正的硬件IP核，并且您可以轻松地检查自适应算法模型与原始代码。
除了接口之外，打算在处理器上运行的算法很少在硬件上开箱即用，因此您需要进行修改。 
有一个很好的综合 
Eilert



以下为原文

Hi,
two months is not much time, but besides the fact that you have to implement several algorithms (and connect them to a system?) it would be interesting for you to look at the performance goals.
 
Has it to be highest possible performance? Then forget it. Your designers need to test different approaches, which costs time.
 
Is the performance goal moderate?  Get the EDK and use a MicroBlaze or PowerPC and just compile the algorithms. 
 
Or if you like it the "no risk no fun" way...use a C-Synthesis tool. This way you can provide true hardware IP-Cores and you can easily check the adapted algorithm models vs. the original code. 
Besides the interfaces, algorithms that are intended to run on processors rarely work out-of-the-box on hardware, so you need to do modifications.
 
  Have a nice synthesis
    Eilert