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我现在是阿根廷国立科技大学的博士生。我目前正在对CY8C9466PXI PSOC的模拟部分进行仿真,以评估测试方法的适用性。为了提高模拟精度,我想问一下,如果你能提供我关于下列参数的信息(或者获得它们的方法):
SC内部的开关和电容器阵列内的开关,特别是嵌入式运算放大器的开/关电阻仿真模型(SPICE)或允许我开发行为级仿真模型的信息。模拟多路复用器,特别是开/关电阻。NCES。 以上来自于百度翻译 以下为原文 I'm currently a PhD Student at National University of Technology, Argentina. I'm currently working on simulations of the analog sections of the CY8C29466-PXI PSoC, for evaluating the applicability of test methods. In order to improve the simulations accuracy I kindly ask, if you could provide me information about the following parameters (or a way to get them):
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您想要的一些信息可以在各种设备和组件数据表中找到。对于大多数用户来说,开关电阻和绝对电容值并不重要,因为重要的是电路在选定时钟速率下的安顿程度。但是,作为指南,单元块中的电容器值是70 FF。我在一篇早期文章(5年前)中错误地指出,该值为50 FF。这些都是典型的值,但在大多数应用程序和大多数客户中,再简单不过了。我知道你想做模拟。所以这些数字很重要。关于SCBORD开关电阻约10KOHM。
运算放大器的增益约为90分贝。在高功率和高偏置下,单位增益带宽约为5.4 MHz,每个功率减小步骤将GBW粗略地切割成一半,因此: P= H,B=H,GBW=5.4兆赫 P= H,B=L,GBW=4 MHz(估计) p= m,b=h,gbw=3.1兆赫 P=M,B=L,GBW=2.5 MHz(估计) P=L,B=H,GBW=015 MHz(估计) P=L,B=L,GBW=0.75兆赫 记住,opopp不能去外面,必须缓冲。 模拟输出缓冲器具有1的增益和0.55伏的转换速率/使用到100 pF负载。 缓冲电阻图形输出电阻为2欧姆。 您可以从直流增益和GBW为OPAP和缓冲器构建标准SPICE模型。 运算放大器带宽和转换速率在VSS和VDD附近变得更差(更低), 在SC块中,开关电阻只影响稳定时间,而不影响直流精度。 MUX的电阻等于约12千欧。这是从规定的MUX电容和带宽计算的。 这应该让你开始。如果你有更多的问题,我很乐意帮忙。 Dennis Seguine(最长服务PSoC应用工程师) 以上来自于百度翻译 以下为原文 Some of the information you want can be found in various device and component datasheets. For most users, the switch resistances and absolute capacitor values don't matter, because what matters is how well the circuit settles at the selected clock rate. But, as a guide, the unit capacitor value in the SCBlocks is 70 fF. I stated incorrectly in an earlier post (5 years ago) that the value was 50 fF. These are typical values, but to say it again, in most applications and most customers, it simply doesn't matter. I understand that you want to do simulations. So these numbers are important. Figure on SCBlock switch's resistance about 10kohm. The opamp has gain of about 90 dB. The unity gain bandwidth is approximately 5.4 MHz at high power and high bias, each power reduction step cuts the GBW roughtly in half, so: P=H,B=H, GBW = 5.4 MHz P=H,B=L, GBW = 4 MHz (estimated) P=M,B=H, GBW = 3.1 MHz P=M,B=L, GBW = 2.5 MHz (estimated) P=L,B=H, GBW = 015 MHz (estimated) P=L, B=L, GBW = 0.75 MHz Remember, the opamps can't go to the outside and must be buffered The analog output buffers have a gain of 1.00 and a slew rate of 0.55 V/use into a 100 pF load. Figure output resistance of buffer at 2 ohms. You can construct a standard SPICE model from the DC gain and the GBW for both opamp and buffer. The opamp bandwidth and slew rate get worse (lower) near Vss and Vdd, In the SC blocks, switch resistance affects only settling time, not DC accuracy. Mux on-resistance is equal to about 12 kohms. This is computed from stated mux capacitance and bandwidth. This should get you started. If you have further questions, I am happy to help. ---- Dennis Seguine (longest serving PSoC applications engineer) |
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xiaohongchen615 发表于 2019-1-4 08:20 非常感谢你,Dennis seg。你提供的信息使我能够验证假设并得出关于它们的有力结论。一旦研究结果出来,我将与开发者社区分享它们。 Emanuel Dri 以上来自于百度翻译 以下为原文 Thank you so much Dennis seg. The information you've provided enables me to validate hypothesis and generate robust conclusions about them. As soon as the research results be come out, I'll be sharing them with the Developer Community. ----Emanuel Dri |
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伊曼纽尔:当你准备出版并想进行评论时,或者如果你有任何持续的问题,我很乐意帮忙。如果你想把预先发布的资料保留在这个论坛上,请直接联系我在SEG@ CyPress网站上。
丹尼斯 以上来自于百度翻译 以下为原文 Emanuel: When you are ready to publish and would like a review, or if you have any continuing questions, I am happy to help. If you want to keep pre-published material out of this forum, contact me directly at seg@cypress.com. ---- Dennis |
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