mipi-csi2-rx示例设计许可证错误

您好@sridhargunnam，
我确认您需要以下许可证（所有许可证均可用作硬件评估或免费（TPG）许可证）：
-  MIPI CSI2
-  VPSS
-  HDMI
-  MIPI DSI TX
-  TPG
我写了AR＃70308（可能在几天后在线）来捕获这些信息。
请注意，您不需要HDMI许可证即可构建BD，因此您可以在生成比特流之前生成并删除HDMI IP。
如果您使用的是Windows操作系统：
确保使用非常短的路径。
否则，您可能会看到GAMMA LUT和Demosaic IP的错误。
我所做的是生成BD然后以非常短的名称保存项目（我在我的C：驱动器下直接使用了项目名称“X”）
在使用硬件评估许可证时，您应该看到AR＃70165（也适用于MIPI子系统）
如果在这个问题上一切都很清楚，请将响应标记为关闭线程的解决方案。
最好的祝福，
弗洛朗
产品应用工程师 - 视频和嵌入式
FlorentProduct应用工程师 -  Xilinx威廉希尔官方网站 支持EMEA ------------------------------------------
--------------------------------------------------
----------------------------不要忘记回复，kudo，并接受作为解决方案。
在原帖中查看解决方案



以下为原文

Hi @sridhargunnam,
 
I confirmed that you need the following licenses (all available as Hardware Evaluation or free (TPG) licenses):
- MIPI CSI2
- VPSS
- HDMI
- MIPI DSI TX
- TPG
 
I have written AR#70308 (might be online in few days) to capture this information.
 
Note that you don't need the HDMI license to build the BD, so you can generate it and remove the HDMI IP before generating the bitstream.
 
If you are using windows OS:

• Make sure you are using a very short path. Else you might see error with the GAMMA LUT and Demosaic IP. What I have done is to generate the BD and then save the project as with a very short name (I have used project name "X" directly under my C: drive)
  
• As you are using a Hardware Evaluation license, you should see AR#70165 (also valid for the MIPI Subsystems)
  

If everything is clear for you on this subject, please kindly mark a response as solution to close the thread.
 
Best Regards,
 
Florent
Product Application Engineer - Video and Embedded
Florent
Product Application Engineer - Xilinx Technical Support EMEA
------------------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
View solution in original post

@sridhargunnam
您可以在tcl控制台中运行以下命令，并确保所有IP都是最新的：
report_ip_status
如果未更新IP，请在tcl控制台中运行以下命令：
upgrade_ip [get_ips]
问候
罗希特
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将Kudos发送给您认为有用且回复的帖子.------------------------------------
--------------------------------------------------
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---------------------------------------------请注意 - 请注明
答案为“接受为解决方案”，如果提供的信息是有帮助的。给予您认为有用并回复导向的帖子。感谢K--
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以下为原文

@sridhargunnam
 
Can you run the below command in the tcl console and make sure all the IPs are up to date:
report_ip_status
 
If IPs are not updated, run the below command in the tcl console:
upgrade_ip [get_ips]
 
Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
 
Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

None


以下为原文

Thanks for the reply.
 
The IP are up to date. Do you think there any other issues? 
 
One thing I observed is that when customizing the IP, I didn't see the tab for board, which is present in the figures shown in the documentation. Please find them in the attachments. 
 
I was trying to use mipi_csi2_rx with IMX274 camera sensor. I instantiated the IP in vivado, did "generate output products", then tried to open the example design project, as I am unsure of all the connections to this IP block. Do you think there is a better way to use these IP's? The mipi_csi2_rx IP documentation is not clear on how to build example design. 
 
 
report_ip_status 
-------------------------------------------------------------------------------------------------------------------------------------------------------------
IP Status Summary
1. Project IP Status
--------------------
Your project uses 12 IP. Some of these IP may have undergone changes in this release of the software. Please review the recommended actions.
More information on the Xilinx versioning policy is available at www.xilinx.com.
Project IP Instances
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Instance Name | Status | Recommendation | Change | IP Name | IP | New Version | New | Original Part |
| | | | Log | | Version | | License | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| mipi_csi2_rx_subsystem_0 | Up-to-date | No changes required | *(1) | MIPI CSI-2 Rx | 3.0 | 3.0 | Purchased | xczu9eg-ffvb1156-2-e |
| | | | | Subsystem | | | | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_phy_0 | Up-to-date | No changes required | *(2) | MIPI D-PHY | 4.0 | 4.0 | Included | xczu9eg-ffvb1156-2-e |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_r_sync_0 | Up-to-date | No changes required | *(3) | Processor System | 5.0 | 5.0 (Rev. 12) | Included | xczu9eg-ffvb1156-2-e |
| | | | | Reset | (Rev. | | | |
| | | | | | 12) | | | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_rx_0 | Up-to-date | No changes required | *(4) | MIPI CSI-2 Rx | 1.0 | 1.0 (Rev. 6) | Purchased | xczu9eg-ffvb1156-2-e |
| | | | | Controller | (Rev. | | | |
| | | | | | 6) | | | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_vfb_0_0 | Up-to-date | No changes required | Change | Video Format | 1.0 | 1.0 (Rev. 8) | Included | xczu9eg-ffvb1156-2-e |
| | | | Log not | Bridge | (Rev. | | | |
| | | | available | | 8) | | | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_phy_0_hssio_rx | Up-to-date | No changes required | *(5) | High Speed | 3.2 | 3.2 (Rev. 2) | Included | xczu9eg-ffvb1156-2-e |
| | | | | SelectIO Wizard | (Rev. | | | |
| | | | | | 2) | | | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_vfb_0_0_axis_converter | Up-to-date | No changes required | *(6) | AXI4-Stream Data | 1.1 | 1.1 (Rev. 13) | Included | xczu9eg-ffvb1156-2-e |
| | | | | Width Converter | (Rev. | | | |
| | | | | | 13) | | | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_vfb_0_0_fifo | Up-to-date | No changes required | *(7) | FIFO Generator | 13.2 | 13.2 | Included | xczu9eg-ffvb1156-2-e |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| mipi_csi2_rx_ctrl_v1_0_6_fc_322048 | Up-to-date | No changes required | *(8) | FIFO Generator | 13.2 | 13.2 | Included | xczu9eg-ffvb1156-2-e |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| mipi_csi2_rx_ctrl_v1_0_6_fifo0 | Up-to-date | No changes required | *(9) | FIFO Generator | 13.2 | 13.2 | Included | xczu9eg-ffvb1156-2-e |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| mipi_csi2_rx_ctrl_v1_0_6_fifo1 | Up-to-date | No changes required | *(10) | FIFO Generator | 13.2 | 13.2 | Included | xczu9eg-ffvb1156-2-e |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| mipi_csi2_rx_ctrl_v1_0_6_fifo2 | Up-to-date | No changes required | *(11) | FIFO Generator | 13.2 | 13.2 | Included | xczu9eg-ffvb1156-2-e |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
*(1) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/mipi_csi2_rx_subsystem_v3_0/doc/mipi_csi2_rx_subsystem_v3_0_changelog.txt
*(2) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/mipi_dphy_v4_0/doc/mipi_dphy_v4_0_changelog.txt
*(3) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(4) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/mipi_csi2_rx_ctrl_v1_0/doc/mipi_csi2_rx_ctrl_v1_0_changelog.txt
*(5) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/high_speed_selectio_wiz_v3_2/doc/high_speed_selectio_wiz_v3_2_changelog.txt
*(6) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axis_dwidth_converter_v1_1/doc/axis_dwidth_converter_v1_1_changelog.txt
*(7) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/fifo_generator_v13_2/doc/fifo_generator_v13_2_changelog.txt
*(8) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/fifo_generator_v13_2/doc/fifo_generator_v13_2_changelog.txt
*(9) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/fifo_generator_v13_2/doc/fifo_generator_v13_2_changelog.txt
*(10) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/fifo_generator_v13_2/doc/fifo_generator_v13_2_changelog.txt
*(11) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/fifo_generator_v13_2/doc/fifo_generator_v13_2_changelog.txt
-------------------------------------------------------------------------------------------------------------------------------------------------------------
 
 
Below is the log for update_ip command:
 
upgrade_ip [get_ips mipi_*]
WARNING: [Coretcl 2-1042] No IP was identified for upgrade.
 

关于我得到的错误的一些额外信息。
当我为MIPI_CSI2_RX_subsystem打开示例IP设计时，我得到了缺少块的以下设计。
你能帮我怎么办吗？
谢谢，
斯里达尔



以下为原文

Some extra information on the error I am getting. 
 
When I open example IP Design for MIPI_CSI2_RX_subsystem, I get following design with missing blocks. Can you help me how to proceed? 
 
Thanks, 
Sridhar

您好@sridhargunnam，
MIPI CSI2示例设计是一个完整的设计，它使用了几个需要许可证的xilinx IP：
CSI2 RX用于连接传感器，但VPSS用于处理（并需要许可证）。
要输出视频，使用DSI TX IP以及HDMI IP（两者都需要许可证）。
您需要（至少）以下硬件评估许可证来生成CSI2 RX示例设计：
-MIPI CSI2
-  VPSS
-  HDMI
-  MIPI DSI TX
您可能还需要TPG的许可证，但它是免费的完整许可证。
您的案例中缺少的第一个许可证是MIPI DSI，但如果您没有所需的所有许可证，则可能会在以后遇到其他问题。
文档不清楚MIPI CSI2示例设计需要哪些许可。
我将报告此更新文档，我将为此编写答复记录。
亲切的问候，
弗洛朗
FlorentProduct应用工程师 -  Xilinx威廉希尔官方网站 支持EMEA ------------------------------------------
--------------------------------------------------
----------------------------不要忘记回复，kudo，并接受作为解决方案。



以下为原文

Hi @sridhargunnam,
 
The MIPI CSI2 Example design is a full design which uses several xilinx IPs which requires a license:

 
The CSI2 RX is used to connect with the sensor but then the VPSS is used for processing (and requires a license).
 
And to output the video, the DSI TX IP is used as well as the HDMI IP (and the both require a license).
 
You need (at least) the following HW evaluation licenses to generate the CSI2 RX example design:
-MIPI CSI2
- VPSS
- HDMI
- MIPI DSI TX
 
You might also require a license for the TPG but it is a free full license.
 
The first license missing in your case is the MIPI DSI but you might have other issues later if you don't have all the licenses required.
 
The documentation is not clear about which licencing are needed for the MIPI CSI2 example design. I will report this to have the documentation updated and I will write an Answer Record for this.
 
Kind Regards,
 
Florent
Florent
Product Application Engineer - Xilinx Technical Support EMEA
------------------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.

您好@sridhargunnam，
我确认您需要以下许可证（所有许可证均可用作硬件评估或免费（TPG）许可证）：
-  MIPI CSI2
-  VPSS
-  HDMI
-  MIPI DSI TX
-  TPG
我写了AR＃70308（可能在几天后在线）来捕获这些信息。
请注意，您不需要HDMI许可证即可构建BD，因此您可以在生成比特流之前生成并删除HDMI IP。
如果您使用的是Windows操作系统：
确保使用非常短的路径。
否则，您可能会看到GAMMA LUT和Demosaic IP的错误。
我所做的是生成BD然后以非常短的名称保存项目（我在我的C：驱动器下直接使用了项目名称“X”）
在使用硬件评估许可证时，您应该看到AR＃70165（也适用于MIPI子系统）
如果在这个问题上一切都很清楚，请将响应标记为关闭线程的解决方案。
最好的祝福，
弗洛朗
产品应用工程师 - 视频和嵌入式
FlorentProduct应用工程师 -  Xilinx威廉希尔官方网站 支持EMEA ------------------------------------------
--------------------------------------------------
----------------------------不要忘记回复，kudo，并接受作为解决方案。



以下为原文

Hi @sridhargunnam,
 
I confirmed that you need the following licenses (all available as Hardware Evaluation or free (TPG) licenses):
- MIPI CSI2
- VPSS
- HDMI
- MIPI DSI TX
- TPG
 
I have written AR#70308 (might be online in few days) to capture this information.
 
Note that you don't need the HDMI license to build the BD, so you can generate it and remove the HDMI IP before generating the bitstream.
 
If you are using windows OS:

• Make sure you are using a very short path. Else you might see error with the GAMMA LUT and Demosaic IP. What I have done is to generate the BD and then save the project as with a very short name (I have used project name "X" directly under my C: drive)
  
• As you are using a Hardware Evaluation license, you should see AR#70165 (also valid for the MIPI Subsystems)
  

If everything is clear for you on this subject, please kindly mark a response as solution to close the thread.
 
Best Regards,
 
Florent
Product Application Engineer - Video and Embedded
Florent
Product Application Engineer - Xilinx Technical Support EMEA
------------------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.

谢谢@florentwfor的详细回复。
在需要时购买个人许可证可能会妨碍我们的设计时间。
是否有文档可以让我们了解图像处理中最常用的不同IP核？
你知道我是否有可以购买的捆绑式包装盒吗？
我是研究生，许可证的资金有限。
所以我也需要考虑价格点。
（如果有学生研究人员的特别优惠，请告诉我们。）
谢谢，
斯里达尔



以下为原文

Thank you @florentw for the detailed response. 
 
 
Buying individual license as and when required may hinder our design time.
 
Is there a documentation which gives us an idea of different IP cores most used in Image processing? Do you know if there is a bundled license package that I can purchase?
 
I am a research student and funds for the license are limited. So I need to look in terms of price point as well. (Please let us know if there are any special offers for student researchers.)
 
Thanks,
Sridhar
 
 
 

您好@sridhargunnam，
这是一个不同的问题。
你能否关闭这个线程（将最佳响应标记为解决方案）并在DSP和视频板中打开一个新线程？
我会尽力回答。
问候，
弗洛朗
FlorentProduct应用工程师 -  Xilinx威廉希尔官方网站 支持EMEA ------------------------------------------
--------------------------------------------------
----------------------------不要忘记回复，kudo，并接受作为解决方案。



以下为原文

Hi @sridhargunnam,
 
This is a different question. Could you close this thread (mark the best response a solution) and open a new thread in the DSP and Video board?
 
I will try to answer.
 
Regards,
 
Florent
Florent
Product Application Engineer - Xilinx Technical Support EMEA
------------------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.

嗨，
我正在尝试编译MIPI CSI-2开发应用程序示例，并得到几个错误，这些错误导致我发表这篇文章，并帮助我通过所有步骤直到生成位文件。
为了生成一个位文件（支持HDMI输出），看起来我需要HDMI IP许可证，我设法从Xilinx获得硬件评估许可证（将在未来3个月内过期）但在更新许可证后，使用report_ip_status返回Design_Linking
禁止使用表示比特流生成的许可证。
我的问题是：我是否需要购买HDMI TX IP许可才能生成位文件？
谢谢



以下为原文

Hi,
I am trying to compile MIPI CSI-2 Development Application Example, and get several errors which lead me to this post, and help me go thru all step until generate bit file. In order to generate a bit file (witch support HDMI output), look like I need a license for HDMI IP, I manage to get Hardware Eval license from Xilinx (which will expired around next 3 months) but after update license, using report_ip_status return Design_Linking license which mean bit stream generate is prohibited.
 
My question is: do I need to buy a license for HDMI TX IP in order to generate bit file?
 
Thanks
 

HI @andrewngo，
不，您可以使用HDMI示例设计生成示例设计。
请在安装和许可委员会中创建一个新主题，以询问评估许可证无效的原因。
注意：我正在关闭这个主题，因为它已经解决了。
问候，
FlorentProduct应用工程师 -  Xilinx威廉希尔官方网站 支持EMEA ------------------------------------------
--------------------------------------------------
----------------------------不要忘记回复，kudo，并接受作为解决方案。



以下为原文

HI @andrewngo,
 
No you can generate the example design with a HDMI example design.
 
Please create a new topic in the Installation and Licensing board to ask why the evaluation license is not working.
 
Note: I am closing this topic as it was already solved.
 
Regards,
Florent
Product Application Engineer - Xilinx Technical Support EMEA
------------------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.