即使处于相同的时钟区域，Vivado也会抛出错误“BUFG和IO在不同的时钟区域”

我在vivado 2016.3中看到了以下地方的错误
错误：[放置30-675]支持全局时钟的IO引脚和BUFG对的次优放置。如果此子设计可接受此子优化条件，则可以使用.xdc文件中的CLOCK_DEDICATED_ROUTE约束降级此消息
警告
但是，强烈建议不要使用此覆盖。
这些示例可以直接在.xdc文件中使用，以覆盖此时钟规则。
FPGA_clk_rtc_IBUF_inst / IBUFCTRL_INST（IBUFCTRL.O）被锁定到IOB_X1Y136
fpga_clk_rtc_IBUF_BUFG_inst（BUFGCE.I）由clockplacer临时放置在BUFGCE_X0Y67上
上述错误可能与其他连接的实例有关。
以下是一份清单
所有相关的时钟规则及其各自的实例。
时钟规则：rule_bufgce_bufg_conflict
状态：通过
规则描述：一对中只有2个可用站点中的一个（BUFGCE或BUFGCE_DIV / BUFGCTRL）可以是
同时使用
fpga_clk_rtc_IBUF_BUFG_inst（BUFGCE.O）由clockplacer临时放置在BUFGCE_X0Y67上
解决方案：如果出现以下情况，可以使用两者之间的专用路由路径：（a）具有全局时钟功能的IO（GCIO）位于支持GCIO的站点上（b）BUFG与GCIO位于同一设备组中
销。
必须同时满足上述两个条件，否则可能导致时钟插入延迟时间更长且更不可预测。请查看设备中BUFG和IO的放置情况



以下为原文

I am seeing the the below place error in vivado 2016.3

ERROR: [Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fpga_clk_rtc_IBUF_inst/O] >fpga_clk_rtc_IBUF_inst/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X1Y136fpga_clk_rtc_IBUF_BUFG_inst (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y67The above error could possibly be related to other connected instances. Following is a list of all the related clock rules and their respective instances.Clock Rule: rule_bufgce_bufg_conflictStatus: PASS Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can beused at the same timefpga_clk_rtc_IBUF_BUFG_inst (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y67Resolution: A dedicated routing path between the two can be used if: (a) The global clock-capable IO (GCIO) is placed on a GCIO capable site (b) The BUFG is placed in the same bank of the device as the GCIO pin. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays.Please look into the placing of the BUFG and IO in the device