Vivado实施错误：功耗优化

加速设计周期实施阶段的能力至关重要，设计人员需要做三件事：
用于综合，布局，布线和物理优化的最佳编译工具允许设计人员最大限度地利用硅器件的方法Vivado Design Suite提供了最佳的实现工具，在性能，运行时和内存消耗方面具有显着优势，我们将介绍
下面的一些原因。
但是，如果给出不切实际的设计，最好的工具仍然会很困难，因此，方法对于提供可以让您更快地在更大和更高性能设计上融合的优势非常重要。
Xilinx在UG949，UltraFAST设计方法学中编制了大量方法学建议。
方法建议的核心是Vivado提供的世界级分析和报告功能。
这些报告允许设计人员从报告交叉探测原理图和设备视图以及推断对象的RTL代码中的确切行。
时序分析引擎包括高度可定制的查询，可以调试时序收敛挑战。
以下列出了有助于设计人员加快实施的重要报告：
方法检查和DRC（设计规则检查）时钟域交叉和时钟交互报告时间约束向导（创建干净约束）设计分析报告（了解设计复杂性和拥塞）控制集reportPipeline分析（如果添加了流水线阶段则测量Fmax改进）Notepad ++
Vivado®DesignSuite分析布局布线威廉希尔官方网站 通过同时优化多个变量提供更可预测的设计收敛：定时（T）恶意软件，还可以互连相关指标，如拥塞（C）和线路长度（W）。
分析放置器将Vivado设计套件与众不同，以保持领先一代.FileZilla下图说明了Vivado Design Suite分析解决的多变量成本函数示例。



以下为原文

The ability to accelerate the implementation phase of the design cycle is of critical importance, and to get there designers need 3 things:
Best in class compilation tools for synthesis, place, route, and physical optimization
Methodology that allows designers to extract the most out of the silicon devices
The Vivado Design Suite delivers the best implementation tools with significant advantages in performance, runtime and memory consumption, and we will cover some of reasons for that below. But the best tools will still struggle if given unrealistic designs, and therefore methodology is very important to deliver the benefits that will allow you to converge more quickly on larger and higher performance designs. Xilinx has compiled an extensive list of methodology recommendations in UG949, UltraFAST Design Methodology. At the heart of the methodology recommendations is world class analysis and reporting capabilities delivered by Vivado. These reports allow the designer to cross-probe from the report to the schematics and the device view as well as the exact line in the RTL code where the object was inferred. The timing analysis engine includes highly customizable queries that makes debugging timing closure challenges possible. Here is a list of important reports that will help designers accelerate implementation:
Methodology Checks and DRCs (design rule checks)
Clock Domain Crossing and Clock Interaction Reports
Timing Constraints Wizard (create clean constraints)
Design Analysis Report (understand design complexity and congestion)
Control Set report
Pipeline Analysis (to gauge Fmax improvement if pipeline stages added) Notepad++
The Vivado® Design Suite Analytical Place and Route technology delivers more predictable design closure by concurrently optimizing for multiple variables: timing (T) Malwarebytes but also interconnect related metrics such as congestion (C) and wire length (W). The analytical placer sets the Vivado Design Suite apart to stay a generation ahead. FileZilla The graph below illustrates an example of a multi-variable cost function solved analytically by the Vivado Design Suite.

嗨，@ mhmontazeri61，
你有没有提到下面的讨论？
https://forums.xilinx.com/t5/Vivado-TCL-Community/Vivado-Tcl-4-131-Power-Optimization-exception/m-p/511265#M2055
https://www.xilinx.com/support/answers/68659.html
你能试试最新版的Vivado吗？
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-----------------------不要忘记回答，kudo，并接受为解决方案.-------------
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以下为原文

Hi, @mhmontazeri61 ,
Have you referred to the below discussion?
https://forums.xilinx.com/t5/Vivado-TCL-Community/Vivado-Tcl-4-131-Power-Optimization-exception/m-p/511265#M2055
https://www.xilinx.com/support/answers/68659.html
 
Could you try the latest Version of Vivado?
 
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Don't forget to reply, kudo, and accept as solution.
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