在综合和实施中遗漏了一些IP

嗨@ behzad34，
你能检查一下最初的综合运行的runme.log文件吗？
如果有一些逻辑修整，这应该表明一些警告。
该文件的默认位置是in.runs / synth_x。
问候，Prathik -----------------------------------------------
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以下为原文

Hi @behzad34,
 
Can you please check the runme.log file of the synthesis run initially? This should indicate some warnings if there is some logic trimming. The default location of the file would be in .runs/synth_x.
 
Regards,
Prathik
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感谢您的答复。
我检查了你提到的文件，但在文件中找不到任何“timm”或“remove”字样。
但仍有一些模块没有实现。



以下为原文

Thanks for your response. I checked the file you mentioned and couldn't find any "timm" or "remove" words in the file. But still some of modules are not implemented.

你好@ behzad34
尝试使用ARhttps：//www.xilinx.com/support/answers/58616.html中描述的方法启用详细报告。
查看合成并查看逻辑是如何推断的。
对于在Implementation（opt_design）中执行的优化，请参阅UG904。
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi @behzad34
 
Try the method described in AR https://www.xilinx.com/support/answers/58616.html to enable verbose reporting.
 
Look at the synthesized and see how the logic is inferred. For optimizations performed in Implementation (opt_design) refer to UG904.
Thanks,
Deepika.
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你好
我检查了报告，在“信息”部分找到了一堆修剪消息。
例如。：
[选项31-54] Cell没有负载并被删除：Multiplyxbip_pipe_v3_0_3_viv__parameterized15 Forces_ins / MulFn / U0 / i_synth / MULT.OP / EXP / COND_DET_B / EXP_DET_LUT.EXP_ALL_ONE_DEL / i_pipe。
[选项31-60]由于恒定输入引脚，单元优化为常数0：R和D，单元格：next_incident_ins / divideoutaA_incident3d84 / U0 / i_synth / DIV_OP.SPD.OP / MANT_DIV / RT [9] .MANT_DEL / i_pipe /
opt_has_pipe.first_q_reg [9]。
[选项31-58]由于输入引脚优化为导线的单元：I0和I1，单元：interface_ins / float2fix_c_inst / U0 / i_synth / FLT_TO_FIX_OP.SPD.OP / ALIGN_Z_D / MUX_LOOP [2] .OTHER_LEVELS.DO_CHUNKS [0]
.LUT6_STRUCT_MUX.MUX1。
但在我的设计中，单元格的输出连接到其他地方，我不知道为什么要修剪它们。
正如我所提到的，在一些设计模块中，最后更新RAM是目标。
RAM应该在另一个模块中读取。
从网表中我看到我写的RAMS没有在模块中实现，有时在读取RAM的模块中实现。
可以吗？
您是否认为RAM应该在写入RAM的模块中实现？
非常感谢



以下为原文

Hi
 
I have checked the report and found a bunch of trimming messages in the "info" section. e.g.:
 
 

• [Opt 31-54] Cell has no loads and is removed: Multiplyxbip_pipe_v3_0_3_viv__parameterized15 Forces_ins/MulFn/U0/i_synth/MULT.OP/EXP/COND_DET_B/EXP_DET_LUT.EXP_ALL_ONE_DEL/i_pipe.
  
• [Opt 31-60] Cell optimized to a constant 0 due to constant input pins: R, and D, cell: next_incident_ins/dividedoutaA_incident3d84/U0/i_synth/DIV_OP.SPD.OP/MANT_DIV/RT[9].MANT_DEL/i_pipe/opt_has_pipe.first_q_reg[9].
  
• [Opt 31-58] Cell optimized to a wire due to input pins: I0, and I1, cell: interface_ins/float2fix_c_inst/U0/i_synth/FLT_TO_FIX_OP.SPD.OP/ALIGN_Z_D/MUX_LOOP[2].OTHER_LEVELS.DO_CHUNKS[0].LUT6_STRUCT_MUX.MUX1.
  

 
But in my design the output of the cells are connected to somewhere else, I don't know why they are being trimmed.
 
As I mentioned, in some of designed modules updating a RAM at the end is the target. And the RAM is supposed to read in another module. From the netlist I see that the RAMS that I am writing to is not implemented in the module and sometimes is implemented in the module which reads the RAM. Is it ok? Don't you think the RAM should be implemented in the module that is writing the RAM as well?
 
thanks a lot