完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
大家好,
我是Vivado的新手。 我想提取已实现设计的LUT名称,但我没有找到合适的tcl命令。 以上来自于谷歌翻译 以下为原文 Hi every body, I am new with Vivado. I want to extract LUT names of the implemented design but I did not find an appropriate tcl command. |
|
相关推荐
5个回答
|
|
你好@ farzian
要提取已实现设计的LUT名称,请打开已实现的设计并在tcl控制台中运行以下命令: show_objects -name find_1 [get_cells -hierarchical -filter {PRIMITIVE_TYPE = ~LUT。*。*}] 您将获得所有LUT的列表及其名称。 问候 罗希特 RegardsRohit ------------------------------------------------- ---------------------------------------------请注意 - 请注明 答案为“接受为解决方案”,如果提供的信息是有帮助的。给予您认为有用并回复导向的帖子。感谢K-- -------------------------------------------------- ---------------------- 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Hi @farzian To extract LUT names of the implemented design, Open the implemented design and run the below command in the tcl console: show_objects -name find_1 [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ LUT.*.* } ] You will get the list of all the LUTs along with their names. Regards Rohit Regards Rohit ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- View solution in original post |
|
|
|
你好@ farzian
要提取已实现设计的LUT名称,请打开已实现的设计并在tcl控制台中运行以下命令: show_objects -name find_1 [get_cells -hierarchical -filter {PRIMITIVE_TYPE = ~LUT。*。*}] 您将获得所有LUT的列表及其名称。 问候 罗希特 RegardsRohit ------------------------------------------------- ---------------------------------------------请注意 - 请注明 答案为“接受为解决方案”,如果提供的信息是有帮助的。给予您认为有用并回复导向的帖子。感谢K-- -------------------------------------------------- ---------------------- 以上来自于谷歌翻译 以下为原文 Hi @farzian To extract LUT names of the implemented design, Open the implemented design and run the below command in the tcl console: show_objects -name find_1 [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ LUT.*.* } ] You will get the list of all the LUTs along with their names. Regards Rohit Regards Rohit ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
|
|
|
嗨@ farzian,
您可以打开已实现的设计 - >查找(ctrl + f) - >选择PREMITIVE TYPE作为LUT,只有您可以找到相应的tcl命令。如果您点击确定,您将获得带有其单元格的LUT名称列表 单元引脚数。作为参考,我附上了快照。 谢谢和RegardsAsit ----------------------------------------------- ---------------------------------------------请将帖子标记为 一个答案“接受为解决方案”,以防它有助于解决您的查询。如果一个帖子引导到解决方案,请给予赞誉。 以上来自于谷歌翻译 以下为原文 Hi @farzian, You can Open Implemented design --> find (ctrl +f) --> select PREMITIVE TYPE as LUT and there only you can find the corresponding tcl command. If yoo click on OK you will get the list of LUT names with their cells and cell pin count. For your reference I have attached the snapshot. Thanks and Regards Asit -------------------------------------------------------------------------------------------- Please mark the post as an answer "Accept as solution" in case it helped resolve your query. Give kudos in case a post in case it guided to the solution. |
|
|
|
我不明白如何解释表达式:= ~LUT。*。*有人可以解释一下这个意思吗?谢谢
以上来自于谷歌翻译 以下为原文 I didn't understand how to interpret the expression : =~ LUT.*.* can someone explain the meaning? thanks |
|
|
|
你好@ pumaju1808
请为此查询打开一个新主题。 问候 罗希特 RegardsRohit ------------------------------------------------- ---------------------------------------------请注意 - 请注明 答案为“接受为解决方案”,如果提供的信息是有帮助的。给予您认为有用并回复导向的帖子。感谢K-- -------------------------------------------------- ---------------------- 以上来自于谷歌翻译 以下为原文 Hi @pumaju1808 Please open a new thread for this query. Regards Rohit Regards Rohit ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
|
|
|
只有小组成员才能发言,加入小组>>
2511 浏览 7 评论
2880 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2337 浏览 9 评论
3430 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2518 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
2627浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
671浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
536浏览 1评论
822浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2025-3-7 03:28 , Processed in 1.288963 second(s), Total 55, Slave 49 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191