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我的环境: - Vivado 2015.03版 - FPGA器件xcvu440 我想超级mygration(xc7v2000 - > xcvu440),但错过了write_bitstream流程中的错误消息,如下所示: 错误:[DRC 23-20]规则违规(ADEF-911)SIM_DEVICE_arch_mismatch - 实例上的SIM_DEVICE值= / U_P_DDR_CLOCK_GEN/u_idelayctrl_REPLICATED_0已从“7SERIES”更改为“ULTRASCALE”以匹配当前的FPGA架构。 要使功能仿真与硬件行为相匹配,应在源网表中更改SIM_DEVICE的值。 我该怎么办才能解决这个问题? 以上来自于谷歌翻译 以下为原文 Hello My environment: -- Vivado 2015.03 version -- FPGA device xcvu440 I want to ultrascale mygration(xc7v2000 -> xcvu440), but miss the error message at write_bitstream flow, in the below: ERROR: [DRC 23-20] Rule violation (ADEF-911) SIM_DEVICE_arch_mismatch - The value of SIM_DEVICE on instance ../U_P_DDR_CLOCK_GEN/u_idelayctrl_REPLICATED_0 was changed from '7SERIES' to 'ULTRASCALE' to match the current FPGA architecture. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. What do i can resolve this issue? |
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3个回答
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嗨@ quincyq2003
Vivado 2015.1 DRC从UltraScale设备系列开始,在bitgen时执行新策略。 此错误消息是bitgen时间之前的警告,但为了确保使用正确的模型进行模拟,生成比特流时消息将成为错误。您需要在设计中正确设置此属性以确保正确的模拟结果。 请检查您的源代码并更改idelay_ctrl中的SIM_DEVICE 谢谢,维杰----------------------------------------------- ---------------------------------------------请将帖子标记为 一个答案“接受为解决方案”,以防它有助于解决您的查询。如果一个帖子引导到解决方案,请给予赞誉。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Hi @quincyq2003 Vivado 2015.1 DRC is enforcing a new policy at bitgen time beginning with the UltraScale device family. This error message is a warning before bitgen time, but to assure you simulated with correct models, the message becomes an error when you generate bitstreams. You will need to set this attribute correctly in your design to ensure correct simulation results. Please check your source code and change the SIM_DEVICE in the idelay_ctrl Thanks,Vijay -------------------------------------------------------------------------------------------- Please mark the post as an answer "Accept as solution" in case it helped resolve your query. Give kudos in case a post in case it guided to the solution.View solution in original post |
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嗨@ quincyq2003
Vivado 2015.1 DRC从UltraScale设备系列开始,在bitgen时执行新策略。 此错误消息是bitgen时间之前的警告,但为了确保使用正确的模型进行模拟,生成比特流时消息将成为错误。您需要在设计中正确设置此属性以确保正确的模拟结果。 请检查您的源代码并更改idelay_ctrl中的SIM_DEVICE 谢谢,维杰----------------------------------------------- ---------------------------------------------请将帖子标记为 一个答案“接受为解决方案”,以防它有助于解决您的查询。如果一个帖子引导到解决方案,请给予赞誉。 以上来自于谷歌翻译 以下为原文 Hi @quincyq2003 Vivado 2015.1 DRC is enforcing a new policy at bitgen time beginning with the UltraScale device family. This error message is a warning before bitgen time, but to assure you simulated with correct models, the message becomes an error when you generate bitstreams. You will need to set this attribute correctly in your design to ensure correct simulation results. Please check your source code and change the SIM_DEVICE in the idelay_ctrl Thanks,Vijay -------------------------------------------------------------------------------------------- Please mark the post as an answer "Accept as solution" in case it helped resolve your query. Give kudos in case a post in case it guided to the solution. |
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可以安全地忽略此警告消息。
但是您可以使用超级设备重新创建项目。 您可以尝试在SIM_DEVICE中手动将目标设备从7系列更改为超级系列 谢谢和RegardsBalkrishan ----------------------------------------------- ---------------------------------------------请将帖子标记为 一个答案“接受为解决方案”,以防它有助于解决您的查询。如果一个帖子引导到解决方案,请给予赞誉。 以上来自于谷歌翻译 以下为原文 This warning message can be safely ignored. however you can recreate the project with ultrascale device . You may try with manually changing target device from 7 series to ultrascale in SIM_DEVICEThanks and Regards Balkrishan -------------------------------------------------------------------------------------------- Please mark the post as an answer "Accept as solution" in case it helped resolve your query. Give kudos in case a post in case it guided to the solution. |
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