使用synplify和生成器网表文件合成VIRTEX 7时报告严重警告

现在来解决严重的警告。
虽然有两个警告，但他们真的抱怨同样的事情。
在某些情况下（不是这个），第一条消息可能是无害的，如果它适用于在旧架构和新架构之间具有直接模拟的单元。
IDELAY和IDELAYCTRL不是这种情况。
这些单元在7系列和UltraScale器件中具有完全不同的功能。
虽然这些工具已经尽力将7系列的功能映射到UltraScale，但行为仍然会有很大不同。
我不建议你像这样离开这个设计。
您需要阅读UltraScale（UG571）中IDELAY和IDELAYCTRL的功能。
然后，您需要确切了解原始7系列设计中IDELAY的用途，并根据UltraScale IDELAY的功能设计新机制。
从一个到另一个的“机械”平移不太可能满足设计的原始要求。
Avrum
在原帖中查看解决方案



以下为原文

 
 
Now to address the critical warnings.
 
While there are two warnings, they are really complaining about the same thing. In some cases (not this one) the first message can be harmless, if it applies to a cell that has a direct analogue between the old architecture and the new. This is not the case for the IDELAY and IDELAYCTRL. These cells have radically different functionality in the 7 series and the UltraScale devices. While the tools have done their best to map the functionality of the 7 series to the UltraScale, the behavior will still be pretty different. I would not recommend you leave the design like this.
 
You need to read up on the functionality of the IDELAY and IDELAYCTRL in the UltraScale (UG571). You then need to figure out exactly what the IDELAY was being used for in the original 7-series design, and design a new mechanism based on the capabilities of the UltraScale IDELAY. A "mechanical" translation from one to the other is not likely to meet the original requirements of the design.
 
Avrum
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现在来解决严重的警告。
虽然有两个警告，但他们真的抱怨同样的事情。
在某些情况下（不是这个），第一条消息可能是无害的，如果它适用于在旧架构和新架构之间具有直接模拟的单元。
IDELAY和IDELAYCTRL不是这种情况。
这些单元在7系列和UltraScale器件中具有完全不同的功能。
虽然这些工具已经尽力将7系列的功能映射到UltraScale，但行为仍然会有很大不同。
我不建议你像这样离开这个设计。
您需要阅读UltraScale（UG571）中IDELAY和IDELAYCTRL的功能。
然后，您需要确切了解原始7系列设计中IDELAY的用途，并根据UltraScale IDELAY的功能设计新机制。
从一个到另一个的“机械”平移不太可能满足设计的原始要求。
Avrum



以下为原文

 
 
Now to address the critical warnings.
 
While there are two warnings, they are really complaining about the same thing. In some cases (not this one) the first message can be harmless, if it applies to a cell that has a direct analogue between the old architecture and the new. This is not the case for the IDELAY and IDELAYCTRL. These cells have radically different functionality in the 7 series and the UltraScale devices. While the tools have done their best to map the functionality of the 7 series to the UltraScale, the behavior will still be pretty different. I would not recommend you leave the design like this.
 
You need to read up on the functionality of the IDELAY and IDELAYCTRL in the UltraScale (UG571). You then need to figure out exactly what the IDELAY was being used for in the original 7-series design, and design a new mechanism based on the capabilities of the UltraScale IDELAY. A "mechanical" translation from one to the other is not likely to meet the original requirements of the design.
 
Avrum

你好，@ avrumw
在下面的严重警告中。
什么是SIM_DEVICE意味着什么？
严重警告[网表29-345]类型为“IDELAYCTRL”的实例“IDELAYCTRL_inst”上的SIM_DEVICE值为“7SERIES”;
它正在被改变以匹配当前的FPGA架构'ULTRASCALE'。
要使功能仿真与硬件行为相匹配，应在源网表中更改SIM_DEVICE的值。
未能正确设置SIM_DEVICE将阻止此设计生成比特流。



以下为原文

Hello, @avrumw
 
 
In the below critical warning.
 
What is the SIM_DEVICE mean?
 
Critical Warning [Netlist 29-345] The value of SIM_DEVICE on instance 'IDELAYCTRL_inst' of type 'IDELAYCTRL' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ULTRASCALE'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. Failure to set the SIM_DEVICE appropriately will prevent bitstream generation for this design.

什么是SIM_DEVICE意味着什么？
在一些不同的系列中存在一些Xilinx原语。
虽然它们大致相同，但它们的功能之间可能存在细微差别。
在综合方面，没有歧义，综合工具知道你要映射到哪个设备。
但是，当您模拟设计时，模拟工具（可能是Vivado模拟器，或任何第三方模拟器中的任何一个）实际上并不了解“设备”。
对于仿真，Xilinx提供单个仿真库，其中包括所有威廉希尔官方网站 中所有Xilinx原语的功能描述;
这允许您（例如）模拟其中包含两个FPGA的设计 - 即使FPGA来自不同的系列（即同一板上的Spartan-6和Kintex-7）。
但是，对于存在在不同族中具有不同行为的原语的情况，模拟器需要知道用于特定实例的行为。
这是SIM_DEVICE参数的作用 - 它仅影响基元的模拟模型，因此模拟对参数指定的设备的行为正确。
例如，RAMB18E1和RAMB36E1原语存在于V5，V6和7系列器件中。
执行模拟时，模拟工具只能访问RAMB18E1的一个模拟模型。
为了知道它是否应该像V5，V6或7系列RAM（可能有细微差别），仿真模型具有SIM_DEVICE参数 - 在V5设计中，所有实例的参数应设置为VIRTEX5，in
V6设计VIRTEX6，7系列设计7_SERIES。
在您的情况下，IDELAYCTRL原语被标记。
同样，这个原语存在于多个家庭中。
因此，对于模拟，必须将其设置为正确的值。
但是对于综合，这些工具知道你的目标是ULTRASCALE，但它找到了原语（可能手动实例化），SIM_DEVICE设置为7_SERIES，或者未指定 - 如果未指定，则使用默认值，即7_SERIES（不是
记录在任何地方，但可以在$ XILINX / Vivado // data / verilog / src / unisims / IDELAYCTRL.v中的仿真模型中看到。
由于这种不一致性（参数的值和实际用于合成的系列），它会发出此严重警告。
Avrum



以下为原文

What is the SIM_DEVICE mean?
 
There are some Xilinx primitives that exist in several different families. While they are largely the same, there may be subtle differences between their functionality.
 
When it comes to synthesis, there is no ambiguity, the synthesis tool knows what device you are mapping to.
 
However, when you simulate the design, the simulation tool (which may be the Vivado simulator, or any of a number of 3rd party simulators), don't actually know anything about "device". For simulation, Xilinx provides a single simulation library, which includes functional descriptions of all the Xilinx primitives found in all technologies; this allows you (for example) to simulate a design that has two FPGAs in it - even if the FPGAs are from different families (i.e. a Spartan-6 and a Kintex-7 on the same board).
 
However, for those cases where there is a primitive that has different behaviors in different families, the simulator needs to know which behavior to use for a particular instance. This is the role of the SIM_DEVICE parameter - it affects the simulation model of the primitive only, so that simulation behaves correctly for the device specified by the parameter.
 
As an example, the RAMB18E1 and RAMB36E1 primitive has existed in the V5, V6 and 7 series devices. When you perform simulation, the simulation tools will have access to only one simulation model for the RAMB18E1. In order to know if it should behave like a V5, V6 or 7 series RAM (which may have subtle differences), the simulation model has the SIM_DEVICE parameter - in a V5 design, the parameter for all instances should be set to VIRTEX5, in a V6 design VIRTEX6, and in a 7 series design 7_SERIES.
 
In your case, the IDELAYCTRL primitive is being flagged. Again, this primitive has existed in multiple families. So, for simulation, it is essential that it be set to the correct value. But for synthesis, the tools know you are targeting ULTRASCALE, but it found the primitive (presumably manually instantiated) either with the SIM_DEVICE set to 7_SERIES, or not specified - if unspecified, it uses the default, which is 7_SERIES (which isn't documented anywhere, but can be seen in the simulation model itself in $XILINX/Vivado//data/verilog/src/unisims/IDELAYCTRL.v). Because of this inconsistency (the value of the parameter and the family actually being used for synthesis), it issues this critical warning.
 
Avrum