如何确保在Vivado实现阶段没有优化逻辑模块资源？

嗨，
opt_design修剪了设计中未连接的逻辑。
因此，如果要修剪的元素的连通性不合适，请检查合成设计。
如果您希望工具不修剪某些特定逻辑，则可以添加DONT_TOUCH约束。
有关语法详细信息，请参阅http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug912-vivado-properties.pdf的第135页。
谢谢，
迪皮卡。
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以下为原文

Hi,
 
The opt_design trims the unconnected logic in the design. So please check the synthesized design if the connectivity of the elements getting trimmed is proper or not.
 
If you want the tool not to trim some specific logic then you can add DONT_TOUCH constraint. Refer to page-135 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug912-vivado-properties.pdf for syntax details.
 
Thanks,
Deepika.
Thanks,
Deepika.
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你好 
非常感谢您的回复 。 
现在，在合成设计中，被修剪的元素的连通性是合适的。合成是正常的，资源利用也是正常的，但是在实施阶段，大部分资源都被优化掉了。我想知道如何解决问题，保证逻辑模块资源
在Vivado实施阶段没有优化？
为什么在Vivado实现阶段优化逻辑模块资源？ 
谢谢



以下为原文

Hi
      Thank you very much for your reply .
      Now  in vivado the synthesized design the connectivity of the elements getting trimmed is proper.So synthesis is normal,resource utilization is also normal ,however in the implementation phase,most of the resources are optimized away.I want to know how to solve the problem for  ensuring the logic module resources are not optimized  in the  Vivado implementation stage? why are  the logic module resources  optimized  in the  Vivado implementation stage?
     Thanks
     

嗨，非常感谢您的回复。
现在在vivado合成设计中，被修剪的元素的连通性是正确的。所以合成是正常的，资源利用也是正常的，但是在实施阶段，大部分资源都被优化掉了。我想知道如何解决问题
确保逻辑模块资源未在Vivado实施阶段进行优化？
为什么在Vivado实现阶段优化逻辑模块资源？
谢谢



以下为原文

Hi
      Thank you very much for your reply .
      Now  in vivado the synthesized design the connectivity of the elements getting trimmed is proper.So synthesis is normal,resource utilization is also normal ,however in the implementation phase,most of the resources are optimized away.I want to know how to solve the problem for  ensuring the logic module resources are not optimized  in the  Vivado implementation stage? why are  the logic module resources  optimized  in the  Vivado implementation stage?
     Thanks

嗨，
你能分享后合成检查点，以便我们检查吗？
打开合成设计并在TCL控制台中运行write_checkpoint命令以生成检查点。
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi,
 
Can you share the post synthesis checkpoint so that we can check it?
 
Open synthesized design and run write_checkpoint command in TCL console to generate the checkpoint.
 
Thanks,
Deepika.
Thanks,
Deepika.
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嗨，转到实施板。
谢谢，维杰-----------------------------------------------
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以下为原文

Hi,
Moving to implementation board.Thanks,Vijay
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你好 
非常感谢您的回复。 
转向实施板？
我很抱歉，我没有解决移动到实施板的方法。你能给我详细的信息。 
谢谢。



以下为原文

Hi
    Thank you very much for your reply.
    Moving to implementation board?  I am  Sorry,I don't unstand   means  of   moving to implementation board.Can you give me detailed information.
   Thanks.

嗨@ zhangwei0814
根据技能组合，Xilinx论坛中有不同的主板。
Yor查询与实现有关，因此我将您的主题移至正确的板上。
谢谢，维杰-----------------------------------------------
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以下为原文

Hi @zhangwei0814 
There differnt boards in Xilinx forums depending on the skillsets. Yor query is related to implementation and hence I moved your topic to correct board.
Thanks,Vijay
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您的ISE综合和实施是真的，最后资源利用分析报告是正常的。
现在在Vivado中，在实现逻辑优化（opt_design）的第一步（实现）中投入大量资源来优化模块（建议逻辑单元不加载），但是当ISE实现尚未优化时，现在
如何确保逻辑模块资源在Vivado实现阶段没有得到优化？现在在合成设计中，被修剪元素的连通性是正确的。合成是正常的，资源利用也是正常的，但在实施阶段，大多数
对资源进行了优化。我想知道如何解决问题，以确保在Vivado实现阶段不优化逻辑模块资源？
为什么逻辑模块资源在Vivado实现阶段进行了优化？谢谢！



以下为原文

Hi
The ISE synthesis and implementation are true, finally resource utilization analysis report is normal. Now in the Vivado, in the first step(Implementation) to realize the logic optimization (opt_design) put a lot of resources to optimize away the module (suggests logical unit not load), but when the ISE implementation has not been optimized away, now how to ensure the logic module resources are not optimized in the Vivado implementation stage?
Now in vivado the synthesized design the connectivity of the elements getting trimmed is proper.So synthesis is normal,resource utilization is also normal ,however in the implementation phase,most of the resources are optimized away.I want to know how to solve the problem for ensuring the logic module resources are not optimized in the Vivado implementation stage? why are the logic module resources optimized in the Vivado implementation stage?
Thanks!