如何将实时输入同步到CM4处理器时钟？

嗨，安得烈，
我可以问更多的信息吗？
你想同步什么样的信号？
有什么时间限制吗？你需要识别多长时间的脉搏？
基本上，时钟是同步的，因为用于产生UDB中所有时钟的默认时钟源是CKKY-PII，它来自源于M4核心（CKLYFAST）的CKKYHF0。如果大于100MHz，则必须将CKLY-PURI除以2。
亲切的问候，
阿希姆



     以下为原文
  Hi Andrew,
 
May I ask for more information.
What kind of signal do you want to synchronize?
Any timing restrictions? How long is the pulse you need to identify?
 
Basically the clocks are in synch already as the default clock source used to generate all the clocks in the UDBs is Clk_peri which is derived from Clk_HF0 that also sources the M4 core (Clk_Fast). If it is greater than 100MHz then Clk_Peri has to be divided by 2.

 
kind regards,
Achim

OK UDB是通用数字块，对吗？上面的图形显示了由M4核心使用的PLL输出。然而，它显示100MHz，而我认为M4核心是150 MHz（从数据表）。第二，什么是克拉克？佩里？这在上面的图形中显示为2分频器后的M4时钟。我假设它是时钟外围设备。这意味着我与它同步吗？我抓取一个同步块，同步块的时钟是CKKY-PII？
另外，它可能是我不需要同步器，因为所有输入都已经与处理器时钟同步，亚稳态已经最小化。状态寄存器显示一个时钟。这是干什么用的？
我附上了一个示意图，显示每个输入的同步块。我希望这不是必要的。
WorkStudio01.CyWrk.CaseV01.Zip
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     以下为原文
  Ok UDB is Universal Digit Blocks, correct? The graphic above shows a PLL output used by the M4 core. However, it is showing 100MHz and I thoughtM4 core was 150MHz (from the Datasheet). Second, what is Clk_Peri? This is shown in  the above graphic as the M4 clock after a /2 divider. I assume it is clock peripheral. Does this mean I synchronize to it? I grab a Sync block and the clock for the Sync block is Clk_Peri?
 
Also, it could be that I don't need a synchronizer, because all input are already synchronized to the processor clock and metastability is already minimized. The status register shows a clock. What is it for?
 
I have attached a schematic showing a sync block for each input. I am hoping this is not necessary.

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嗨，安得烈，
是的，UDB =通用数字块。
CKKY-PARI是在示意图中使用的默认引用的时钟。所以，是的，你的描述。
所以不需要同步。
如果寄存器中的位用“粘性”代替“透明”模式，则使用状态寄存器的时钟。在“粘性”模式下，输入在该时钟的上升沿采样，并且在读取寄存器时仅被清除。
PS:是的，150 MHz是M4内核的最大值，上面只是默认值，它们可以在“设计范围资源”“时钟”选项卡中更新。
当做，
阿希姆



     以下为原文
  Hi Andrew,
 
Yes, UDB = Universal Digital Block.
Clk_Peri is the clock that is the default reference being used in the schematic view. So yes, to your description.
So synchronisation should not be needed.
 
The Clock of the Status registers is used if the bits in the register are used in "sticky" instead of "transparent" mode. In "sticky" mode the input is sampled on rising edge of that clock and only cleared when the register is read.
 
PS: Yes, 150MHz is the max. of the M4 core, above are just the default values and they can be updated in the "Design Wide Resources" "Clocks" Tab.
 
regards,
Achim