如何避免闩锁？

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niras wrote:

Hi,
Thanks to both of you, but I can't assign fd_out <= fd_out, becuase it is declared as an o/p in entity, Is there any problem declare the item as a buffer in the top most module?

 
 
 
You don't need to assign fd_out in the way you suggest (to avoid the latch) if you use a synchronous process for your logic.
 
 
 

Second, the given code is from a combinational process. In this project I seperate all combinational logic and sequencial logic in to two different processes. In the sequencial process only update registers using the next value given by the combinational logic. But the o/p are available (because o/p are not registered, but all i/p are registered) as soon as the clock applied.

 
 
 
And people wonder why I say: NEVER USE THE TWO-PROCESS STATE MACHINE MODEL.
Simple answer: make everything synchronous and these problems go away.
 

 
But if fd_out is used to update a register in the sequential process, it may solve the problem, but there will be a one clock delay, and to avoid this I need to detect the condition one clock ahead (count = 3) and so one more comparator is required for the same.

 
 
 
So there's a pipeline delay. That's life. The solution is obvious (you point it out!) and you've got an FPGA with lots of logic. Don't make things difficult for yourself. Do it right.
 
 
 

Finally, I used a synchronous reset, so I put reset in the combinational logic, to reset all next register values, I think the reset may not put in the sequencial part.

 
 
 
The synch reset isn't the problem. The combinatorial process is the problem.
 
 
 

My approach is problematic? but I only faced the problem with fd_out, all other things are o.k.