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Xilinx不会合成
A = B C
我从Coregen实例化一个带符号的算术分频器模块，设备为Virtex 4。
Virtex 5没有coregen分频器模块。
ISE 10.2给出了翻译错误，ISE 9.2没有给出错误。
提前致谢，
Siby Thachil
我希望你的代码是：
A 以下为原文
123xilinx123 wrote:
'ABC_sig_div_16_5_2clk' is an signed arithmetic divider with dividend (16 bits), divisor (5 bits) in 2 clock cycle.
Xilinx doesnot synthesize
A = B C
I instantiated a signed arithmetic divider module from Coregen with device as Virtex 4.
Virtex 5 doesnot have coregen divider module.
ISE 10.2 gives error in translate, ISE 9.2 doesnot give error.
Thanks in advance,
Siby Thachil
I hope your code is:
A <= B / C;
and not
A = B C
as these statements are different (the second is not legal VHDL).
=a
----------------------------Yes, I do this for a living.
/6 
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