dspic33启用全局和外设中断

在XC16的我的版本（1.34）中，用户指南解释了在“14.7”中启用/禁用中断应该在您的版本中是相同的吗？



      以下为原文

    In my version (1.34) of XC16, the User's Guide explains that in section '14.7 ENABLING/DISABLING INTERRUPTS'
Should be the same in your version?

启用模块或外部中断。每秒钟中断第五秒。定时器5中断：您可以使用状态寄存器禁用所有中断。中断优先级（SRIPITS IPL＝7）



      以下为原文

    Enable the module or external interrupt.
Interrupt every fifth of a second.
T5CON = _T5CON_TCKPS0_MASK|_T5CON_TCKPS1_MASK|_T5CON_TON_MASK;
PR5 = 31250 - 1;
TMR5 = 0;
IFS1bits.T5IF = 0;
IEC1bits.T5IE = 1;
Interrupt on timer 5:
void __attribute__((interrupt, no_auto_psv)) _T5Interrupt(void){
    IFS1bits.T5IF = 0;
}


You can disable all interrupts using the Status Register.Interrupt Priority Level  (SRbits.IPL = 7)

PIC24/DSSPIC33没有像PIC18那样的全局中断启用/禁用位。但是PIC24E/DSPIC33 E做。



      以下为原文

    The PIC24/dsPIC33 don't have a global interrupt enable/disable bit like the PIC18.  But the PIC24E/dsPIC33E do.

嗨，谢谢你提供的信息。我以前从未见过这种差别。



      以下为原文

    Hi,
 
Thanks for this info. I had never seen this difference before ;=)
Regards

IPL位可以用来启用/禁用所有中断，或者基于中断级别进行选择。“DISI”指令非常有用。



      以下为原文

    The IPL bits can be used to enable/disable all interrupts, or selectively based on the interrupt level.
 
Also "DISI" instruction is very helpful.

嗨，我的观点的最大优点是启用/验证GIE是一个原子指令；



      以下为原文

    Hi,
The BIG advantage to my opinion is that enabling/dsabling GIE is an atomic instruction ;=)
Regards

IPL操作也可以是原子的。比如说，你可以使用IOR将所有3位设置成一个指令中的0B111（这禁止中断）。然后，您可以使用和清除一些位来恢复所需的中断级别-这也是原子。您还可以创造性地使用IPL位。比如说，你只能使用较低的2位的IPL（你将有3个不同的中断级别-1,2和3）。通过这种安排，IPL的最高比特将完全按照GIE工作。禁用中断会增加中断等待时间，因此，如果您的设计非常快速和高效，则通常无法承受中断中断。相反的是真实的-如果你能负担得起的禁用中断，你可能不需要把效率推向极限无论如何。在这种情况下，任何方法都是可行的，即使是最麻烦的方法，例如在DISI下操作IPL。



      以下为原文

   


IPL manipulations can be atomic too. Say, you can use IOR to set all 3 bits to 0b111 in one instruction (this disables the interrupts). Then you can use AND to clear some of the bits to restore the required interrupt level - this is atomic too.
 
You can also use IPL bits creatively. Say, you can only use the lower 2 bits of IPL (you'll have 3 distinct interrupt levels - 1,2, and 3). With this arrangement, the highest bit of the IPL will work exactly as GIE.
 
Disabling interrupts increases interrupt latency, so if your design is really fast and efficient you usually cannot afford disabling interrupts at all. Opposite is true too - if you can afford the luxury of disabling interrupts, you probably don't need to push efficiency to the limits anyway. In such cases, any method will work, even the most cumbersome one, such as manipulating IPL while under DISI.