TM4C123x使用知识点：TM4C123系列中避免同时使用AHB和APB总线

这点针对的应该仅仅是GPIO时钟的选择，我也是从TI的国外论坛看到的，数据手册中对这点的描述如下。
 From data sheet tm4c123gh6pm june 12 2014 revision on page 258 (D S -T M 4C 123G H6 P M - 1 5 8 4 2 . 2 7 4 1
S P M S 376E)
Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C
This register controls which internal bus is used to access each GPIO port. When a bit is clear, the
corresponding GPIO port is accessed across the legacy Advanced Peripheral Bus (APB) bus and
through the APB memory aperture. When a bit is set, the corresponding port is accessed across
the Advanced High-Performance Bus (AHB) bus and through the AHB memory aperture. Each
GPIO port can be individually configured to use AHB or APB, but may be accessed only through
one aperture. The AHB bus provides better back-to-back access performance than the APB bus.
The address aperture in the memory map changes for the ports that are enabled for AHB access
(see Table 10-6 on page 660).
Important: Ports K-N and P-Q are only available on the AHB bus, and therefore the corresponding
bits reset to 1. If one of these bits is cleared, the corresponding port is disabled. If any
of these ports is in use, read-modify-write operations should be used to change the
value of this register so that these ports remain enabled.